Kitform Microbee Timeframes

[CheshireNoir]

Hi All,
Feel free to delete this post if inappropriate.
I'm trying to budget my retro-purchases for the rest of this FY.
Is the long rumoured return of Kitform Microbees likely to happen before Christmas? If so I can start putting some $$$ aside for them.

Cheers!

Chesh

[MbeeTech]

Hello Chesh.

We are still working on the Classic-Plus.
Progress has been made over the last few months, but we keep running into problems with the FPGA logic design and battling the xilinx tools.
What we are working on at the moment is the embedded processor that handles the SDcard floppy disk emulation, and also runs as a second processor
allowing the machine to boot and run in 68000 mode as an alternative.
Unfortunately, because of the hassles we've had with the project, we can't give a release date.

[CheshireNoir]

Thanks Ewan,
I appreciate both the update and the honesty.
I'll start setting aside some money for it, but I'll get myself an Amstrad CPC 464 in the meantime :-)

Best of luck with the project. If there's anything I can personally do to assist, let me know!
(I'm probably only useful from a "testing" point of view. My electronics skills tend to stop at "Don't hold the hot end of the soldering iron")

Various 68000 FPGA cores are being actively discussed over on the English Amiga Boards right now. See this thread: http://eab.abime.net/showthread.php?t=100729&page=17 Maybe an opportunity for some cross pollination of ideas?

Chesh

[MbeeTech]

Thanks Chesh.

I do have the 68k core going no problems. Where I run into problems is with the Xilinx map, place and route. Making the smallest of changes to the logic changes the way the place and route tools puts the logic within the FPGA fabric and can totally break the design, not just the related logic. BTW, I'm using the 68Kods core, which works well.

[MbeeTech]

Hi All.
I thought I would post a quick update in regards to the Classic Plus kit.

What I have been doing of late it to convert the FPGA logic design from its Altium Schematic based design entry
to ISE (webpack 14.7) schematic design entry.
Although using Altium Designer as the front end for my FPGA work has been good up until now, with a complex design like this that
needs more constraints added, Altium designer just doesn't allow for more than basic clock constraints.
Moving to entry direct into ISE should allow me to get the problems in the logic design sorted and the project moving ahead.

All the best,

[MbeeTech]

Hi All.
I've just posted an update on the Classic-Plus / 256TC-Plus in regards to sorting out the FPGA.
As in the post above, I did start re-entering the logic design into Xilinx ISE before deciding to make
the change to using Lattice's ECP5 FPGA instead.

More details here :
https://microbeetechnology.com.au/forum/...65#pid1165