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+--- Thread: SINCLAIR QL (/thread-1049.html)
SINCLAIR QL - Graham72 - 11-07-2026
IN 1984 Sir Clive Sinclair launched his multitasking Sinclair QL to counter the Macintosh and IBMPC computers. Over 150,000 were sold in three years. But a weird data storage system* & bad press killed it.
It was an interesting concept that also lives on today in emulation. So I thought can I port the original 2mhz bee to it. And the answer is yes. A Z80 core can be quickly coded and the 6545 can also be emulated. See attached code = flags need to be added.
However, I wont be pursuing it, my 5.29 emulation needs more smoke tests. The 1980s saw many systems that sadly the IBM/Apple behemoths annihlated. But fun to remember what may have been.
Any readers used one?
*I understand the later Samsung tape loops were so over-engineered they still work today.
RE: SINCLAIR QL - fathertedcrilly - 12-07-2026
I might be missing something but the code seems incomplete
Are there supposed to be more attachments ?
Thanks
Tony
RE: SINCLAIR QL - Graham72 - 12-07-2026
Yes, its just the beginning. Flags are needed next. Then 6545. It was just an idle thought.
RE: SINCLAIR QL - someone - 13-07-2026
Why is someone's replay 406 - Not Acceptable?
(13-07-2026, 10:29 PM)someone Wrote: Why is someone's replay 406 - Not Acceptable?
Multi-tasking can be accomplished on a 128K DRAM microbee if you connect up a periodic interrupt to it such as VSYNC to the PIO Port B Bit 7.
You contain the hypervisor code in upper memory (8000-EFFF) and you have at your disposal 3 x 32K DRAM pages at 0000-7FFF to run each task.
One uses the periodic ISR to capture and switch CPU register sets and active DRAM memory page at 0000-7FFF.
One must take care to ensure that the R (Refresh) register is kept intact to ensure that the DRAM remains properly refreshed.
There is however inbuilt I/O resource management that needs be managed or considered.
Someone has demonstrated this concept driving 3 simultaneous instances of MWBASIC working this way on a 128K microbee.
The ROM image remains in upper memory at 8000, with 3 independent MWBASIC programs loaded into each 32K DRAM page.
There's a bit of EDASM & NET Shadow RAM (C000-EFFF) available for use for the hypervisor.
The Z80 RLD & RRD instructions are useful for multitasking because they are instructions that can perform 2 tasks simultaneously as not to create a "Race"condition. (i.e. Change the contents of a nominated memory location and change the contents of the Accumulator).
I.E. Stopping an unwanted Interrupt occurring between CPU instructions to cause a synchronisation issue.
RE: SINCLAIR QL - Graham72 - 17-07-2026
(13-07-2026, 10:29 PM)someone Wrote: Why is someone's replay 406 - Not Acceptable?SICK! I will try this out in my emulator > ultimate stress test. thanks someone!
(13-07-2026, 10:29 PM)someone Wrote: Why is someone's replay 406 - Not Acceptable?
Multi-tasking can be accomplished on a 128K DRAM microbee if you connect up a periodic interrupt to it such as VSYNC to the PIO Port B Bit 7.
You contain the hypervisor code in upper memory (8000-EFFF) and you have at your disposal 3 x 32K DRAM pages at 0000-7FFF to run each task.
One uses the periodic ISR to capture and switch CPU register sets and active DRAM memory page at 0000-7FFF.
One must take care to ensure that the R (Refresh) register is kept intact to ensure that the DRAM remains properly refreshed.
There is however inbuilt I/O resource management that needs be managed or considered.
Someone has demonstrated this concept driving 3 simultaneous instances of MWBASIC working this way on a 128K microbee.
The ROM image remains in upper memory at 8000, with 3 independent MWBASIC programs loaded into each 32K DRAM page.
There's a bit of EDASM & NET Shadow RAM (C000-EFFF) available for use for the hypervisor.
The Z80 RLD & RRD instructions are useful for multitasking because they are instructions that can perform 2 tasks simultaneously as not to create a "Race"condition. (i.e. Change the contents of a nominated memory location and change the contents of the Accumulator).
I.E. Stopping an unwanted Interrupt occurring between CPU instructions to cause a synchronisation issue.