16-06-2026, 12:01 AM
Welcome.
Quick question, just to make sure, when you were checking signals (RESET, CLK, IORQ etc.) did you have both boards (coreboard & baseboard) plugged together?
The Coreboard has the system reset circuit on it. The RESET Key is connected to pin 25 (front most pin) of the right hand 25 way socket strip which then goes to the reset circuit on the coreboard. This generates a Keyboard reset (hold the RESET key down for 1 second to activate) and a 'Power-on Clock '. These get ANDéd together (active low signals) to provide a CPU reset signal.
The left hand side 25 way socket strip (on the coreboard / baseboard) have the Z80 Address Buss, ROM chip select and Z80 data buss on them.
The right hand side 25 way has the Z80 control signals IORQ, MREQ, RD, WR, Clock, JumpLatch + more.
At power on, the CPU should cycle MREQ RD cycles from address 0 to Address 0x7FFF and execute NOP instructions.
When it reaches 0x8000 (first address of the BASIC roms) the ROMcs going active will set JLATCH active, and open up the Z80 data buss to the ROM data and the Z80 should start executing the code in the BASIC rom.
IF you don't see the Z80 doing these cycles at power up then there is something wrong with
* the CPU not getting reset
* BUSREQ active where it shouldn't be
* NMI active where it shouldn't be
* WAIT active where it shouldn't be.
If you do see MREQ RD cycles, but no IORQ cycles, it means that it's not accessing code from the ROM most likely due to
* incorrect addresses (an address line or 2 not pulling all the way up or down due to a faulty output driver or shorted line)
* data buss transceiver (74ls245) not being enabled by the JLATCH signal / ROMcs detection.
* a fault on the data buss, with one or more bits incorrect.
I notice the boards are from Swedish configured Microbees.
The dot clock for the 6545 / screen section should be 13.5 Mhz, not 12Mhz.
Do you have the schematics?
P.S. the first thing I do when looking at these old machines is to get a fine file and ' clean ' the inside and outside edges of the coreboard's 25 way pin strips.
Make sure they are nice and bright, removing any tarnished surface. This seems a little brutal, but the newly cleaned surfaces of the pins on the pinstrip are then
a bit like mini files that after a few insertions and removals into the baseboard sockets, end up cleaning the socket contacts usually enough to get the bee going.
Quick question, just to make sure, when you were checking signals (RESET, CLK, IORQ etc.) did you have both boards (coreboard & baseboard) plugged together?
The Coreboard has the system reset circuit on it. The RESET Key is connected to pin 25 (front most pin) of the right hand 25 way socket strip which then goes to the reset circuit on the coreboard. This generates a Keyboard reset (hold the RESET key down for 1 second to activate) and a 'Power-on Clock '. These get ANDéd together (active low signals) to provide a CPU reset signal.
The left hand side 25 way socket strip (on the coreboard / baseboard) have the Z80 Address Buss, ROM chip select and Z80 data buss on them.
The right hand side 25 way has the Z80 control signals IORQ, MREQ, RD, WR, Clock, JumpLatch + more.
At power on, the CPU should cycle MREQ RD cycles from address 0 to Address 0x7FFF and execute NOP instructions.
When it reaches 0x8000 (first address of the BASIC roms) the ROMcs going active will set JLATCH active, and open up the Z80 data buss to the ROM data and the Z80 should start executing the code in the BASIC rom.
IF you don't see the Z80 doing these cycles at power up then there is something wrong with
* the CPU not getting reset
* BUSREQ active where it shouldn't be
* NMI active where it shouldn't be
* WAIT active where it shouldn't be.
If you do see MREQ RD cycles, but no IORQ cycles, it means that it's not accessing code from the ROM most likely due to
* incorrect addresses (an address line or 2 not pulling all the way up or down due to a faulty output driver or shorted line)
* data buss transceiver (74ls245) not being enabled by the JLATCH signal / ROMcs detection.
* a fault on the data buss, with one or more bits incorrect.
I notice the boards are from Swedish configured Microbees.
The dot clock for the 6545 / screen section should be 13.5 Mhz, not 12Mhz.
Do you have the schematics?
P.S. the first thing I do when looking at these old machines is to get a fine file and ' clean ' the inside and outside edges of the coreboard's 25 way pin strips.
Make sure they are nice and bright, removing any tarnished surface. This seems a little brutal, but the newly cleaned surfaces of the pins on the pinstrip are then
a bit like mini files that after a few insertions and removals into the baseboard sockets, end up cleaning the socket contacts usually enough to get the bee going.