reset key and nmi

[fathertedcrilly]

Hi Tony.
Yes, the RESET key circuit on DRAM based coreboards goes to the NMI pin of the CPU.
The reason for this is that a reset can be performed while not losing DRAM refresh in the process.
Stopping the Z80 via holding RESET low too long, or A BUSREQ/BUSACK cycle that is longer than the
DRAM refresh rate will cause the memory contents to become invalid.  Resetting the CPU also clears the
refresh counter.
To work around this, triggering an NMI to do a software reset keeps the refresh counter going and DRAM
being refreshed to keep it's contents valid.

Cheers

When I get to the DRAM models,  the reset logic will need to be expanded to cater for this

on a related point, Is it safe to say that interrupts really aren't used anywhere on the standard platform save for this and the PIO B RTC bit ( on the PC85 ) ?

Now back to the grindstone.  I forgot to code the EI delay into the core

Thanks
Tony