23-01-2021, 06:57 PM
The /ROMSEL signal is used to enable the Z80 to access the system data bus.
After a reset, the system data bus is isolated from the Z80 CPU and with the pulldown resistor pack on the CPU's data pins presenting a %00 NOP instruction to it so the address bus continually increments until the /ROMSEL is asserted usually by a ROM's /CS (or equivalent) signal (which has been asserted by the address presented on the address bus along with the appropriate control signals such as /MREQ). So with that explained, for MWBASIC, the /ROMSEL is connected to the /CS of the first MWBASIC ROM at address %8000, on a 56K coreboard /ROMSEL is asserted by the /CS of the Boot ROM at address %E000.
#NOTE: ROM assertion is a combination of /CS and /OE. In some designs the /CS is tied low making the /OE being the assertion mechanism, some vice versa and others employing more complicated schemes.
On a DRAM coreboard it works a similarly but with the /NMI signal used in place of the /RESET signal and a short pulse generator to assert the Z80 CPU' s isolation from the data bus.
This was done as a measure to ensure that the Dynamic RAMs would be continually refreshed. If the /RESET signal was used, the DRAM /RFSH signal that refreshes the DRAM would temporarily stop risking the DRAMs from being refreshed and data being lost.
A DRAM coreboard boots up at %8000 allowing it to boot up as a MWBASIC coreboard with ROMS at %8000-%EFFF and RAM at %0000-7FFF or more normally booting up a DRAM coreboard boot ROM (at %8000) such as BN54 that configures the system to emulate a 56K coreboard system with a BIOS at %E000 and RAM at %0000-DFFF.
On a 128K DRAM coreboard, amongst other things, the DRAM is presented as 4 pages of 32K with all pages being presentable at memory address %0000-7FFF and only one at %8000-%FFFF. Upon an /NMI the memory is reset to is default configuration of DRAM at %0000-7FFF (unintuitively page #1 and not #0) and Boot ROM at %8000.
After a reset, the system data bus is isolated from the Z80 CPU and with the pulldown resistor pack on the CPU's data pins presenting a %00 NOP instruction to it so the address bus continually increments until the /ROMSEL is asserted usually by a ROM's /CS (or equivalent) signal (which has been asserted by the address presented on the address bus along with the appropriate control signals such as /MREQ). So with that explained, for MWBASIC, the /ROMSEL is connected to the /CS of the first MWBASIC ROM at address %8000, on a 56K coreboard /ROMSEL is asserted by the /CS of the Boot ROM at address %E000.
#NOTE: ROM assertion is a combination of /CS and /OE. In some designs the /CS is tied low making the /OE being the assertion mechanism, some vice versa and others employing more complicated schemes.
On a DRAM coreboard it works a similarly but with the /NMI signal used in place of the /RESET signal and a short pulse generator to assert the Z80 CPU' s isolation from the data bus.
This was done as a measure to ensure that the Dynamic RAMs would be continually refreshed. If the /RESET signal was used, the DRAM /RFSH signal that refreshes the DRAM would temporarily stop risking the DRAMs from being refreshed and data being lost.
A DRAM coreboard boots up at %8000 allowing it to boot up as a MWBASIC coreboard with ROMS at %8000-%EFFF and RAM at %0000-7FFF or more normally booting up a DRAM coreboard boot ROM (at %8000) such as BN54 that configures the system to emulate a 56K coreboard system with a BIOS at %E000 and RAM at %0000-DFFF.
On a 128K DRAM coreboard, amongst other things, the DRAM is presented as 4 pages of 32K with all pages being presentable at memory address %0000-7FFF and only one at %8000-%FFFF. Upon an /NMI the memory is reset to is default configuration of DRAM at %0000-7FFF (unintuitively page #1 and not #0) and Boot ROM at %8000.