30-11-2020, 04:21 PM
Someone has noticed a design fault with their Cromemco SCC (Single Card Computer).
The design fault consists of using 2 non-buffered signals with a buffered signal as inputs to a logic gate so that an unwanted runt appears on the output.
The runt appears because a simultaneous event occurs on one of the unbuffered signals and the buffered input signal thus creating a simultaneous event becomes 2 distinct events deferred by the propagation time of the buffer.
This runt can be quickly and horribly removed by loading the output signal with a 10nF capacitor to signal ground to stop it from forming.
This value is just enough to remove the runt reliably whilst seemingly having no ill side effects.
The capacitor is connected to IC55 pin 6 (74LS11 - 3 input AND gate).
Examples of the abovementioned fault are often used as laboratory tutorial exercise for introductory Digital Logic training courses.
This fault and solution is similar to the microbee's CRTC LPEN signal bodge fix on the classic models.
The design fault consists of using 2 non-buffered signals with a buffered signal as inputs to a logic gate so that an unwanted runt appears on the output.
The runt appears because a simultaneous event occurs on one of the unbuffered signals and the buffered input signal thus creating a simultaneous event becomes 2 distinct events deferred by the propagation time of the buffer.
This runt can be quickly and horribly removed by loading the output signal with a 10nF capacitor to signal ground to stop it from forming.
This value is just enough to remove the runt reliably whilst seemingly having no ill side effects.
The capacitor is connected to IC55 pin 6 (74LS11 - 3 input AND gate).
Examples of the abovementioned fault are often used as laboratory tutorial exercise for introductory Digital Logic training courses.
This fault and solution is similar to the microbee's CRTC LPEN signal bodge fix on the classic models.