28-11-2020, 07:01 PM
(This post was last modified: 28-11-2020, 09:15 PM by someone.
Edit Reason: Some corrections and additions
)
Here are some notes from someone about some DGZ80 manual schematic errors and omissions.
1. For PCB REV C, the IC4 inverter on page #1 that feeds IC6 pins 4 and 10 uses pins 13 and 12 and not 5 and 6 respectively.
2. Connection details for the S100 DIN and DOUT buffers (81LS97, IC31 and IC32) is missing.
The enable pins of the DIN buffer is driven by IC30, pin 8 (IC7,74LS30)
The enable pins of the DOUT buffer is driven by an inverter (IC11 pin 8) whose input (pin 9) is connected to S100 pin 23 /DOUT DISABLE.
3. S100 pin 23 is pulled up to +5V using R8 (4k7).
4. Connection details for the Z80 address buffers (81LS97, IC20 and IC24) is missing.
The buffer enable pins (pins 1 and 19) of both buffers are driven by inverter (IC11 pin 6) whose input is connected to S100 pin 22 /ADDR DISABLE.
5. S100 pin 22 is pulled up to +5V using R9 (4k7).
6. The onboard memory and I/O is connected to the buffered address bus.
7. The inverter pins that drives pin 4 and 10 of IC 6 is incorrectly shown as pins 5 and 6.
This should read pins 13 and 12 respectively.
8. The RAM and ROM address pins are connected to the buffered Address signals.
9. The bidirectional Data bus pins by the onboard devices are connected directly to the Z80 data bus pins.
10. The 81LS97 Tristate Octal buffers used have a different pin out to the 74LS244 but are functionally equivalent.
11. The DGZ80 provides its own pullup resistors for many S100 control signals.
12. The DGZ80 has an RC network for debouncing the S100 /RESET pin 75.
13. For REV D cards, be aware that PCB traces have been laid so that the POJ address selection DIP switch does not need to be installed for selecting the DGOS D000 address. Remember to cut these 5 PCB traces prior to installing a POJ DIP switch.
14. For REV C cards, mount a 1k resistor on the back of IC17 (74LS125) pin 10 as this is the pull up resistor denoted on the schematic but missing on the PCB for the PWAIT S100 signal (pin 72)
Note: Could be 4k7 for consistency
15. There are 8 pull up resistors (or resistor network) missing for the POJ DIP switch. The PCB relies upon floating input pins to return a logic High which is poor practice.
16. For REV C cards. IC33 and IC36, the schematic diagram (page 5) is incorrect. The PCB is laid out such that IC33 pin 9 is connected to D7 and IC36 pin 9 is connected to D6. Also the POJ DIP switch pins on the schematic for Pins 1 and 2 are reversed.
1. For PCB REV C, the IC4 inverter on page #1 that feeds IC6 pins 4 and 10 uses pins 13 and 12 and not 5 and 6 respectively.
2. Connection details for the S100 DIN and DOUT buffers (81LS97, IC31 and IC32) is missing.
The enable pins of the DIN buffer is driven by IC30, pin 8 (IC7,74LS30)
The enable pins of the DOUT buffer is driven by an inverter (IC11 pin 8) whose input (pin 9) is connected to S100 pin 23 /DOUT DISABLE.
3. S100 pin 23 is pulled up to +5V using R8 (4k7).
4. Connection details for the Z80 address buffers (81LS97, IC20 and IC24) is missing.
The buffer enable pins (pins 1 and 19) of both buffers are driven by inverter (IC11 pin 6) whose input is connected to S100 pin 22 /ADDR DISABLE.
5. S100 pin 22 is pulled up to +5V using R9 (4k7).
6. The onboard memory and I/O is connected to the buffered address bus.
7. The inverter pins that drives pin 4 and 10 of IC 6 is incorrectly shown as pins 5 and 6.
This should read pins 13 and 12 respectively.
8. The RAM and ROM address pins are connected to the buffered Address signals.
9. The bidirectional Data bus pins by the onboard devices are connected directly to the Z80 data bus pins.
10. The 81LS97 Tristate Octal buffers used have a different pin out to the 74LS244 but are functionally equivalent.
11. The DGZ80 provides its own pullup resistors for many S100 control signals.
12. The DGZ80 has an RC network for debouncing the S100 /RESET pin 75.
13. For REV D cards, be aware that PCB traces have been laid so that the POJ address selection DIP switch does not need to be installed for selecting the DGOS D000 address. Remember to cut these 5 PCB traces prior to installing a POJ DIP switch.
14. For REV C cards, mount a 1k resistor on the back of IC17 (74LS125) pin 10 as this is the pull up resistor denoted on the schematic but missing on the PCB for the PWAIT S100 signal (pin 72)
Note: Could be 4k7 for consistency
15. There are 8 pull up resistors (or resistor network) missing for the POJ DIP switch. The PCB relies upon floating input pins to return a logic High which is poor practice.
16. For REV C cards. IC33 and IC36, the schematic diagram (page 5) is incorrect. The PCB is laid out such that IC33 pin 9 is connected to D7 and IC36 pin 9 is connected to D6. Also the POJ DIP switch pins on the schematic for Pins 1 and 2 are reversed.