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New Model Development Updates - MbeeTech - 04-02-2022
Hello All.
A little update.
I was hoping to be able to show off the work that has been happening on the Classic-Plus / 256TC-Plus early this month
in celebration of the 40th anniversary of the release of the kit Microbee.
Let me give you a run down on it.
Firstly, the problems that I've encountered have all been to do with the FPGA logic design.
The original SoDimm module that I designed to go in these models was based on a Xilinx
Spartan 6 FPGA and I proceeded to get the logic design done in schematic form entered via Altium
designer as a front end (which is the method I've used on previous projects). The problem is
that the logic for this design is quite large, and (as I discovered much later) Altium really doesn't
allow for applying timing constraints (clock, async paths, multicycle paths etc. etc.). When ever I'd make a change
to the logic, unrelated parts of the design stopped working.
The only path forward from here was to restart the logic design using the vendor tools instead of Altium.
At the same time, I figured that as I had to restart the logic design I might as well change from Xilinx parts
to Lattice (ECP5) parts for performance and cost benefits.
So, on to restarting the logic design. It has taken months to re-enter the logic into Lattice Diamond in schematic
form (although with more involvement with verilog HDL this time) and get it to meet timing properly. I also have been
running simulation on the design and debugging a few logic errors, but overall the design seems to be working well.
The outputs for the video section all seem to be doing what they should (SYNC, RGB outputs all working, CRTC timing
is correct etc..)
A note on schematic entry for FPGA designs..
Most logic design for FPGA is done purely in HDL coding (verilog or VHDL) these days, and in fact, there are only a few tools
that offer any form of schematic entry now. In my book, schematic entry is still very useful (for me at least) as it helps
visualize the logic in a design, rather than having to dig through lots of code to get an idea of what is supposed to be
happening. I'm a visual person in this regard. It is still necessary to have knowledge on the code beneath the schematic
but to be able to tie it all together visually helps.
So, on to real hardware.
As a stop-gap / trial approach before I committed to a new SoDimm module design (for the Lattice FPGA) I found a pre-made module
that I could press into service with an adapter SoDimm :
![[Image: SmallECP5Mini.GIF]](https://microbeetechnology.com.au/pictures/Classic_Plus/SmallECP5Mini.GIF)
The ECP5Mini (by Josh Johnson) had enough available I/O, so I made an SoDimm board for it to sit on.
The one shown above is built as the HDMI out version.
I had a ' do'h ' moment though when I first assembled the SoDimm carrier board - I plugged the
ECP5Mini in the wrong way around, and subsequently fried the FPGA and SPI flash.
I removed the FPGA and replaced it and all seemed good. Fast forward to testing the logic I'd created
and I found that there were 4 pairs of signals that had shorts on the board. I reflowed the FPGA and got rid of
3 of the shorts, but the forth was stubborn and refused to open. The only thing now was to remove the FPGA
and attempt another. Upon removing the FPGA though, and cleaning up all the pads, it showed that some of
the solder mask had disappeared from the very fine tracks (.125mm width) between the pads (0.41mm pad, 0.8mm pitch)
making it very likely that I would get more shorts if I replaced the FPGA - scrap the board.
I can get another ECP5Mini with a couple of weeks, and then go about modding it again, but I figured, now that I'm happy
with the logic, that I'd be better spending time on getting the proper new SoDimm, for the Lattice part, designed and
prototyped.
So, now, I'm madly designing a new SoDimm around the LFE5U-25, with 2Mb onboard ram and some other bits.
I'm hoping to have the design finished within a week & off to the PCB factory.
Some of the things I've put into the new design :
Backwards compatible Premium Graphics
Extended 4 bit plane graphics (fully dot addressable colour rather than just colour per character cell)
Up to 640 x 256 available in 16 colours from a palette of 4096
Separate foreground and background colour palettes
Support logic for fast fill / copy of the 4 bit plane graphics memory
I'm really excited that this is getting closer and can't wait to show off some screen demos.
I'm hoping this will still be during this month, but time will tell.
RE: Happy 40th Anniversary of the Microbee - someone - 04-02-2022
Thanks for the update Ewan,
Someone's working FPGA microbee was created using Protel DXP2004 back in 2004 and had Protel's founder Nick Martin (also a microbee author & enthusiast) interest and attention.
The FPGA microbee worked great with IDE hard disks and Compactflash cards.
In addition to FPGA development, Protel also provided a real time debuggable Z80 equivalent soft core with assembler and C compiler.
The accompanying Nanoboard hardware was excellent only to be let down by perpetually unresolved software bugs.
Even the mere change of a letter in a signal name was enough to cause a design that worked into a failed mess.
The FPGA and software development portions of Altium Designer were dropped some years ago in favour for a sole focus on PCB design and with that change development was moved from Australia to China.
RE: Happy 40th Anniversary of the Microbee - MbeeTech - 05-02-2022
(04-02-2022, 04:40 PM)someone Wrote: In addition to FPGA development, Protel also provided a real time debuggable Z80 equivalent soft core with assembler and C compiler.
The accompanying Nanoboard hardware was excellent only to be let down by perpetually unresolved software bugs.
Even the mere change of a letter in a signal name was enough to cause a design that worked into a failed mess.
The FPGA and software development portions of Altium Designer were dropped some years ago in favour for a sole focus on PCB design and with that change development was moved from Australia to China.
I've used the protel z80 soft core before, and the soft JTAG debugging / instruments - which were a great feature.
I didn't have the Nanoboard, but did have the original LiveDesign Demo board that had an XC3S400 on it.
I was quite peeved when they dropped support for FPGA development, but now I know more, and about the things that it didn't do well,
I am not so fussed. Besides, it wasn't ever going to support some of the newer players in FPGA.
RE: Happy 40th Anniversary of the Microbee - MbeeTech - 11-02-2022
Another quick update.
The new FPGA board has turned into a 6 layer PCB with .125mm tracks and 0.2mm vias due to the Lattice FPGA
and some other parts having 0.8mm pitch between BGA pads. Routing of the board is going well and I should be
able to post a picture of the 3D model in the next couple of days.
RE: Happy 40th Anniversary of the Microbee - someone - 12-02-2022
(11-02-2022, 10:16 AM)ejwords Wrote: Another quick update.Excellent stuff!
The new FPGA board has turned into a 6 layer PCB with .125mm tracks and 0.2mm vias due to the Lattice FPGA
and some other parts having 0.8mm pitch between BGA pads. Routing of the board is going well and I should be
able to post a picture of the 3D model in the next couple of days.
With your PCB design, it's a good idea to place visible layer markers for all layers to ensure that the PCB has been properly stacked by the PCB manufacturer.
e.g an area of the pcb that you can look through to the light ensure that the layers are in order.
It's also a great idea to keep power planes as close to signal layers to reduce electromagnetic emissions. (e.g. 5mil (thous of an inch) layers).
(The standard stackup for 4 & 6 layer PBs are essentally ineffectual.)
For PCB board design with Signal Integrity and EM compliance considerations, get you hands on books from Eric Bogatin, Henry Ott, Bruce Archambeault & Lee Ritchey.
Practioners and teachers of these techniques include Rick Hartley & Suzy Webb.
Have a look at Robert Feranec's YouTube channel for interviews with the abovementioned experts.
You'll learn things like:
a. it's not the clock speed but the slew rate of the signals being the main consideration for SI and EMC.
b. visualise each signal connection as small loops and keep the size of the loops as small as possible.
c. the oddest things can act as unwanted 1/4 wave antennas transmitting or inducing electrical noise.
d. bypass/decoupling capacitors are not necessarily required.
RE: Happy 40th Anniversary of the Microbee - MbeeTech - 13-02-2022
Quote:With your PCB design, it's a good idea to place visible layer markers for all layers to ensure that the PCB has been properly stacked by the PCB manufacturer.
e.g an area of the pcb that you can look through to the light ensure that the layers are in order.
Yep, agree, great tip where you have the board space to permit it.
I've never had a problem with the Fab houses getting the stackup incorrect. In fact for most jobs they query the stackup
and make sure they are building it right.
3D model as promised
(in the boards' current state : about 50 % routed but with quite a few passives to place still)
![[Image: MB-SO-LFE5U-V10_part_route.JPG]](https://microbeetechnology.com.au/pictures/Classic_Plus/MB-SO-LFE5U-V10_part_route.JPG)
RE: Happy 40th Anniversary of the Microbee - MbeeTech - 25-02-2022
Almost done with the new SO-Dimm module.
Added a more bits (not all will be populated for the Classic Plus).
![[Image: MB-SO-LFE5U-V10_Proto.JPG]](https://microbeetechnology.com.au/pictures/Classic_Plus/MB-SO-LFE5U-V10_Proto.JPG)
RE: Classic Plus Development Updates - MbeeTech - 31-03-2022
Hi All.
Just to keep things a little neater, I split these posts about the Classic Plus development updates off from the Buzzing About -> Happy 40th Anniversary of the Microbee topic.
The 'Microbee Hardware' section of the forum is a better place for it anyway.
RE: Classic Plus Development Updates - MbeeTech - 31-03-2022
Hello all.
The new PCBs for the FPGA module arrived a little while ago now & have been assembled.
Testing is underway at present, and looking o.k. so far. 1 minor oopsicle that needed fixing caused by
late night design (swapped D0 & D1 for the config flash due to [mis]reading the SPI interface names DO is not d0).
Anyway, here's a photo of the fully assembled PCB :
![[Image: MB-SO-LFE5U-V10_proto_full.JPG]](https://microbeetechnology.com.au/pictures/Classic_Plus/MB-SO-LFE5U-V10_proto_full.JPG)
Not a very clear photo, but I'm very happy with the PCBs. I tried a new supplier for these and the boards seem really good
quality with excellent mask and overlay registration. The boards assembled really well too, with only 1 of the boards needing
2 small shorts removed.
Hopefully, in the next week I'll have some photos of the board in-situ doing basic Microbee things.
RE: Classic Plus Development Updates - CheshireNoir - 31-03-2022
Super exciting there, Ewan.
I'll be watching this thread with a lot of interest.
Chesh