04-02-2022, 11:22 AM
Hello All.
A little update.
I was hoping to be able to show off the work that has been happening on the Classic-Plus / 256TC-Plus early this month
in celebration of the 40th anniversary of the release of the kit Microbee.
Let me give you a run down on it.
Firstly, the problems that I've encountered have all been to do with the FPGA logic design.
The original SoDimm module that I designed to go in these models was based on a Xilinx
Spartan 6 FPGA and I proceeded to get the logic design done in schematic form entered via Altium
designer as a front end (which is the method I've used on previous projects). The problem is
that the logic for this design is quite large, and (as I discovered much later) Altium really doesn't
allow for applying timing constraints (clock, async paths, multicycle paths etc. etc.). When ever I'd make a change
to the logic, unrelated parts of the design stopped working.
The only path forward from here was to restart the logic design using the vendor tools instead of Altium.
At the same time, I figured that as I had to restart the logic design I might as well change from Xilinx parts
to Lattice (ECP5) parts for performance and cost benefits.
So, on to restarting the logic design. It has taken months to re-enter the logic into Lattice Diamond in schematic
form (although with more involvement with verilog HDL this time) and get it to meet timing properly. I also have been
running simulation on the design and debugging a few logic errors, but overall the design seems to be working well.
The outputs for the video section all seem to be doing what they should (SYNC, RGB outputs all working, CRTC timing
is correct etc..)
A note on schematic entry for FPGA designs..
Most logic design for FPGA is done purely in HDL coding (verilog or VHDL) these days, and in fact, there are only a few tools
that offer any form of schematic entry now. In my book, schematic entry is still very useful (for me at least) as it helps
visualize the logic in a design, rather than having to dig through lots of code to get an idea of what is supposed to be
happening. I'm a visual person in this regard. It is still necessary to have knowledge on the code beneath the schematic
but to be able to tie it all together visually helps.
So, on to real hardware.
As a stop-gap / trial approach before I committed to a new SoDimm module design (for the Lattice FPGA) I found a pre-made module
that I could press into service with an adapter SoDimm :
![[Image: SmallECP5Mini.GIF]](https://microbeetechnology.com.au/pictures/Classic_Plus/SmallECP5Mini.GIF)
The ECP5Mini (by Josh Johnson) had enough available I/O, so I made an SoDimm board for it to sit on.
The one shown above is built as the HDMI out version.
I had a ' do'h ' moment though when I first assembled the SoDimm carrier board - I plugged the
ECP5Mini in the wrong way around, and subsequently fried the FPGA and SPI flash.
I removed the FPGA and replaced it and all seemed good. Fast forward to testing the logic I'd created
and I found that there were 4 pairs of signals that had shorts on the board. I reflowed the FPGA and got rid of
3 of the shorts, but the forth was stubborn and refused to open. The only thing now was to remove the FPGA
and attempt another. Upon removing the FPGA though, and cleaning up all the pads, it showed that some of
the solder mask had disappeared from the very fine tracks (.125mm width) between the pads (0.41mm pad, 0.8mm pitch)
making it very likely that I would get more shorts if I replaced the FPGA - scrap the board.
I can get another ECP5Mini with a couple of weeks, and then go about modding it again, but I figured, now that I'm happy
with the logic, that I'd be better spending time on getting the proper new SoDimm, for the Lattice part, designed and
prototyped.
So, now, I'm madly designing a new SoDimm around the LFE5U-25, with 2Mb onboard ram and some other bits.
I'm hoping to have the design finished within a week & off to the PCB factory.
Some of the things I've put into the new design :
Backwards compatible Premium Graphics
Extended 4 bit plane graphics (fully dot addressable colour rather than just colour per character cell)
Up to 640 x 256 available in 16 colours from a palette of 4096
Separate foreground and background colour palettes
Support logic for fast fill / copy of the 4 bit plane graphics memory
I'm really excited that this is getting closer and can't wait to show off some screen demos.
I'm hoping this will still be during this month, but time will tell.
A little update.
I was hoping to be able to show off the work that has been happening on the Classic-Plus / 256TC-Plus early this month
in celebration of the 40th anniversary of the release of the kit Microbee.
Let me give you a run down on it.
Firstly, the problems that I've encountered have all been to do with the FPGA logic design.
The original SoDimm module that I designed to go in these models was based on a Xilinx
Spartan 6 FPGA and I proceeded to get the logic design done in schematic form entered via Altium
designer as a front end (which is the method I've used on previous projects). The problem is
that the logic for this design is quite large, and (as I discovered much later) Altium really doesn't
allow for applying timing constraints (clock, async paths, multicycle paths etc. etc.). When ever I'd make a change
to the logic, unrelated parts of the design stopped working.
The only path forward from here was to restart the logic design using the vendor tools instead of Altium.
At the same time, I figured that as I had to restart the logic design I might as well change from Xilinx parts
to Lattice (ECP5) parts for performance and cost benefits.
So, on to restarting the logic design. It has taken months to re-enter the logic into Lattice Diamond in schematic
form (although with more involvement with verilog HDL this time) and get it to meet timing properly. I also have been
running simulation on the design and debugging a few logic errors, but overall the design seems to be working well.
The outputs for the video section all seem to be doing what they should (SYNC, RGB outputs all working, CRTC timing
is correct etc..)
A note on schematic entry for FPGA designs..
Most logic design for FPGA is done purely in HDL coding (verilog or VHDL) these days, and in fact, there are only a few tools
that offer any form of schematic entry now. In my book, schematic entry is still very useful (for me at least) as it helps
visualize the logic in a design, rather than having to dig through lots of code to get an idea of what is supposed to be
happening. I'm a visual person in this regard. It is still necessary to have knowledge on the code beneath the schematic
but to be able to tie it all together visually helps.
So, on to real hardware.
As a stop-gap / trial approach before I committed to a new SoDimm module design (for the Lattice FPGA) I found a pre-made module
that I could press into service with an adapter SoDimm :
The ECP5Mini (by Josh Johnson) had enough available I/O, so I made an SoDimm board for it to sit on.
The one shown above is built as the HDMI out version.
I had a ' do'h ' moment though when I first assembled the SoDimm carrier board - I plugged the
ECP5Mini in the wrong way around, and subsequently fried the FPGA and SPI flash.
I removed the FPGA and replaced it and all seemed good. Fast forward to testing the logic I'd created
and I found that there were 4 pairs of signals that had shorts on the board. I reflowed the FPGA and got rid of
3 of the shorts, but the forth was stubborn and refused to open. The only thing now was to remove the FPGA
and attempt another. Upon removing the FPGA though, and cleaning up all the pads, it showed that some of
the solder mask had disappeared from the very fine tracks (.125mm width) between the pads (0.41mm pad, 0.8mm pitch)
making it very likely that I would get more shorts if I replaced the FPGA - scrap the board.
I can get another ECP5Mini with a couple of weeks, and then go about modding it again, but I figured, now that I'm happy
with the logic, that I'd be better spending time on getting the proper new SoDimm, for the Lattice part, designed and
prototyped.
So, now, I'm madly designing a new SoDimm around the LFE5U-25, with 2Mb onboard ram and some other bits.
I'm hoping to have the design finished within a week & off to the PCB factory.
Some of the things I've put into the new design :
Backwards compatible Premium Graphics
Extended 4 bit plane graphics (fully dot addressable colour rather than just colour per character cell)
Up to 640 x 256 available in 16 colours from a palette of 4096
Separate foreground and background colour palettes
Support logic for fast fill / copy of the 4 bit plane graphics memory
I'm really excited that this is getting closer and can't wait to show off some screen demos.
I'm hoping this will still be during this month, but time will tell.
![[Image: MB-SO-LFE5U-V10_part_route.JPG]](https://microbeetechnology.com.au/pictures/Classic_Plus/MB-SO-LFE5U-V10_part_route.JPG)
![[Image: MB-SO-LFE5U-V10_Proto.JPG]](https://microbeetechnology.com.au/pictures/Classic_Plus/MB-SO-LFE5U-V10_Proto.JPG)
![[Image: MB-SO-LFE5U-V10_proto_full.JPG]](https://microbeetechnology.com.au/pictures/Classic_Plus/MB-SO-LFE5U-V10_proto_full.JPG)
