New Model Development Updates

[someone]

Another quick update.

The new FPGA board has turned into a 6 layer PCB with .125mm tracks and 0.2mm vias due to the Lattice FPGA
and some other parts having 0.8mm pitch between BGA pads.  Routing of the board is going well and I should be
able to post a picture of the 3D model in the next couple of days.

Excellent stuff!

With your PCB design, it's a good idea to place visible layer markers for all layers to ensure that the PCB has been properly stacked by the PCB manufacturer.
e.g an area of the pcb that you can look through to the light ensure that the layers are in order.

It's also a great idea to keep power planes as close to signal layers to reduce electromagnetic emissions. (e.g. 5mil (thous of an inch) layers).
(The standard stackup for 4 & 6 layer PBs are essentally ineffectual.)

For PCB board design with Signal Integrity and EM compliance considerations, get you hands on books from Eric Bogatin, Henry Ott, Bruce Archambeault & Lee Ritchey.
Practioners and teachers of these techniques include Rick Hartley & Suzy Webb.
Have a look at Robert Feranec's YouTube channel for interviews with the abovementioned experts.
You'll learn things like:
 a. it's not the clock speed but the slew rate of the signals being the main consideration for SI and EMC.
 b. visualise each signal connection as small loops and keep the size of the loops as small as possible.
 c. the oddest things can act as unwanted 1/4 wave antennas transmitting or inducing electrical noise.
 d. bypass/decoupling capacitors are not necessarily required.