06-03-2023, 10:27 PM
Hello All.
A bit of an update on the Classic Plus as It's been a while.
Nothing really to 'Show' at this point but there has been a lot of work done
in the FPGA logic to implement:
* M68K softcore processor
* UART module
* TIMER module
* Bus interface unit to both the internal Z80 bus peripherals (CRT controller registers,
screen memories, other system control ports) and external Z80 bus for the M68K processor.
* Floppy disk Emulation logic
* Linear addressing for the M68K processor to access the 4 bit plane graphics
* SDcard interface
It's taken a while to get all that implemented but I'm pretty confident the logic is
pretty much 'Done'. That being said, the design doesn't meet timing at the moment (it has setup & hold time
violations), so I have to work through that. After I have it meeting timing I need to do some simulation to
confirm the design and make sure the M68K core (M68Kods) has been implemented properly. I've used this
core before but in a xilinx environment rather than lattice so I had to re-implement a 16 longword dual port memory
that was a standard part under xilinx.
There are some other items that I'd like to implement in the FPGA, but when I get the above signed off I'll be
finalizing the hardware ready for production.
So, as mentioned, nothing really to show at the moment, but lots still happening.
A bit of an update on the Classic Plus as It's been a while.
Nothing really to 'Show' at this point but there has been a lot of work done
in the FPGA logic to implement:
* M68K softcore processor
* UART module
* TIMER module
* Bus interface unit to both the internal Z80 bus peripherals (CRT controller registers,
screen memories, other system control ports) and external Z80 bus for the M68K processor.
* Floppy disk Emulation logic
* Linear addressing for the M68K processor to access the 4 bit plane graphics
* SDcard interface
It's taken a while to get all that implemented but I'm pretty confident the logic is
pretty much 'Done'. That being said, the design doesn't meet timing at the moment (it has setup & hold time
violations), so I have to work through that. After I have it meeting timing I need to do some simulation to
confirm the design and make sure the M68K core (M68Kods) has been implemented properly. I've used this
core before but in a xilinx environment rather than lattice so I had to re-implement a 16 longword dual port memory
that was a standard part under xilinx.
There are some other items that I'd like to implement in the FPGA, but when I get the above signed off I'll be
finalizing the hardware ready for production.
So, as mentioned, nothing really to show at the moment, but lots still happening.